You (Jonathan) LiComputer Engineering

Open to engineering internships

I build embedded systems from signal to software.

Computer Engineering @ University of Michigan

ESP32 · FPGA · Hardware Integration · Validation

View projects

01 / About

I like working at the hardware–software boundary, especially on problems where physical behavior, logic, and data meet.

My work has taken me from wiring robot control systems and synthesizing FPGA designs to building sensor-driven ESP32 firmware and tracing enterprise workflow data.

Across those settings, the method is consistent: understand the interface, make system state observable, test assumptions, and document a solution others can trust.

01

Embedded systems

Sensor integration, state machines, filtering, communication protocols, and device-side C/C++.

02

Hardware & digital logic

FPGA design, lab instrumentation, circuit prototyping, electrical integration, and fault isolation.

03

Data flow & automation

SQL-backed workflows, Python data collection, HTTP/JSON interfaces, and clear operational logic.

04

Validation & testing

Controlled experiments, regression tests, measurement interpretation, and production-minded verification.

02 / Selected projects

Built, connected, and tested.

Three projects that show how I approach hardware-software systems at different layers.

Phase II · Planned —Target: November 2026

Next: Edge Vision & Sensor Fusion

A focused next step for the prototype—not a completed result.

Add event-triggered camera capture and lightweight on-device classification, then combine visual and distance evidence to reduce false triggers. The final system will be evaluated with classification accuracy, inference latency, and a 24–72 hour reliability test.

02
University of Rochester2025

FPGA Digital Logic Coursework

A ten-lab digital design sequence that built toward one meaningful capstone: a Mealy FSM-based bitstream encryption device implemented on a DE0-CV FPGA.

  • Combinational logic and Verilog foundations
  • Timing, hazards, registers, and state design
  • FSM-based bitstream encryption device
VerilogQuartus IIDE0-CVJTAG
Explore the capstone
03
FIRST Robotics · Team 80152022 — 2024

Robot Electrical Integration

Supported the electrical and vision stack of a competition robot, from controller wiring to subsystem testing and fault isolation.

  • roboRIO and power distribution wiring
  • Limelight setup and debugging
  • Electromechanical subsystem testing
roboRIOLimelightWiringDebugging
Explore the field system

Coursework / ECE 112 Logic Design

From state graph to a working encryption device.

The earlier labs were the foundation, not the portfolio headline: logic gates, Verilog, adders, multiplexers, display drivers, timing and hazards, and counters. The capstone pulled those ideas together into a sequential system that recognizes bit patterns and changes its output mode in real time.

TRIGGER110enter complement mode
RETURN101return to pass-through
MODELMealy FSMoutput depends on state + input
HARDWARED flip-flopsQuartus schematic on DE0-CV
Hand-drawn Mealy finite-state-machine graph with states 000 through 101 and 110 and 101 trigger paths
01 / DESIGN MODELState graph for the Mealy encryptorThe six-state graph tracks partial matches, switches into complemented output after 110, and returns to pass-through after 101.
Quartus schematic implementing the FPGA encryption device with D flip-flops, combinational logic, clock input, and LED output
02 / IMPLEMENTATIONQuartus schematic and board I/OThe design maps the bitstream input, push-button clock, D flip-flop state, and LED output into a synthesizable hardware network.

Engineering loop

Specify → derive → synthesize → verify

BIT PATTERNSSTATE TABLEBOOLEAN LOGICQUARTUSDE0-CV

Starting from the two control sequences, I built the state graph and transition table, derived the flip-flop input equations with Karnaugh maps, translated the logic into Quartus, and tested the behavior both in simulation and on the board.

Report result

End-to-end bitstream validation

The report feeds the ASCII message “MAY 10 8:30” through the FSM and records the transformed byte stream:

INPUT4D 41 59 20 31 30 20 38 3A 33 30OUTPUT4C 41 5A DF CE CF DF C7 C4 34 CF

Figures reproduced from my ECE 112 Lab Report 10. The state graph is my design artifact; the Quartus image is my implementation record. The other labs remain visible as coursework context rather than standalone portfolio projects.

Team 8015 / Robot Electrical Integration

Reliable control-system integration on a competition robot.

From 2022 to 2024, I supported Team 8015’s robot electrical system, focused on reliable control-system integration, fault isolation, vision hardware, and mentoring.

Team 8015 competition robot on the 2023 CHARGED UP field
01 / PLATFORMTeam 8015 competition robotElectrical integration work under real competition constraints.
RESULT2023 Istanbul Regional Champion

My responsibility

Control-system wiring, fault isolation, and mentoring

  • Routed and verified power, CAN, Ethernet, and signal connections.
  • Diagnosed intermittent electrical and interface faults.
  • Configured and troubleshot Limelight hardware.
  • Trained younger team members on control-system architecture.

03 / Experience

Engineering in real operating environments.

Experience spanning industrial automation, technical communication, laboratory equipment, and user-facing troubleshooting.

2025 — 2026Two summer terms

Eaton Corporation · Shanghai, China

Summer 2026

IT Intern — Automation & Data Tools

Extended a low-code platform with custom code and SQL, automated supplier and procurement data collection with Python, and created internal technical training resources.

SQLPythonJavaScriptDocumentation
Summer 2025

IT Intern — Office Automation

Developed and tested multistage business workflows for four factories, tracing approval logic and data flow to diagnose issues before production release.

Low-codeWorkflow logicValidation
Feb — May 2026

University of Rochester · Rochester, NY

Laboratory Teaching Intern — Electricity & Magnetism

Supported experiments with oscilloscopes, multimeters, function generators, power supplies, and circuit components while helping students interpret measurements and experimental error.

InstrumentationRC / RLCTroubleshooting

04 / Toolkit & education

A practical, cross-layer foundation.

Languages

C++ · C · Python · Verilog

Embedded & Digital

ESP32 · I²C · UART · FPGA · RTL · FSM

Hardware & Test

Oscilloscope · DMM · Function Generator · Soldering · Circuit Prototyping

Tools

Git · CMake / CTest · Quartus II

2026 — 2028 expected

University of Michigan

B.S.E. in Computer Engineering

Ann Arbor, Michigan
2024 — 2026

University of Rochester

Coursework in Electrical & Computer Engineering

Transferred to University of Michigan · Dean’s List · Rochester, New York

Relevant coursework

Logic Design · Digital Integrated Circuits · Embedded Control Systems · Computer Organization · Semiconductor Devices · Signals and Systems · Programming and Data Structures

05 / Contact

I'm currently looking for Summer 2027 opportunities in embedded systems, hardware engineering, validation, and test.

The best way to reach me is by email.

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